Apr 3, 2014

PLC-LADDER LOGIC-ATMEGA8


Micro-controller --Atmel AVR ATmega8 28-PDIP'
Crystal frequency---16.000000 MHz 

HOW TO COMPILE AND UPLOAD LDMICRO PROGRAM FOR ATMEGA8



Proteus  simulation  for atmega8


1)Digital input and output

 Pin D1 will be high when a digital high is given at pin D0


LADDER DIAGRAM:

   ||                                  ||
   ||       Xd0              Yd1       ||
 1 ||-------] [--------------( )-------||
   ||                                  ||
   ||                                  ||
   ||                                  ||
   ||------[END]-----------------------||
   ||                                  ||
   ||                                  ||


I/O ASSIGNMENT:

  Name                       | Type               | Pin
 ----------------------------+--------------------+------
  Xd0                        | digital in         | 2
  Yd1                        | digital out        | 3


2) Input negated digital switch
Pin B0 in Microcontroller will be high when a digital low is given at pin B6

LADDER DIAGRAM:

   ||                                  ||
   ||       Xb0              Yb6       ||
 1 ||-------]/[--------------( )-------||
   ||                                  ||
   ||                                  ||
   ||                                  ||
   ||------[END]-----------------------||
   ||                                  ||
   ||                                  ||


I/O ASSIGNMENT:

  Name                       | Type               | Pin
 ----------------------------+--------------------+------
  Xb0                        | digital in         | 27
  Yb6                        | digital out        | 28

3)TON TIMER

The pin RB5 will on after one second delay after program starts

LADDER DIAGRAM:

   ||                                  ||
   ||      Tnew             YRB5       ||
 1 ||--[TON 1.000 s]---------( )-------||
   ||                                  ||
   ||                                  ||
   ||                                  ||
   ||------[END]-----------------------||
   ||                                  ||
   ||                                  ||


I/O ASSIGNMENT:

  Name                       | Type               | Pin
 ----------------------------+--------------------+------
  YRB5                       | digital out        | 19
  Tnew                       | turn-on delay      |


4)XOR Gate

LADDER DIAGRAM:

   ||                                                   ||
   ||       XD0              XD1              YB5       ||
 1 ||-------] [--------------]/[------+-------( )-------||
   ||                                 |                 ||
   ||       XD0              XD1      |                 ||
   ||-------]/[--------------] [------+                 ||
   ||                                                   ||
   ||                                                   ||
   ||                                                   ||
   ||------[END]----------------------------------------||
   ||                                                   ||
   ||                                                   ||


I/O ASSIGNMENT:

  Name                       | Type               | Pin
 ----------------------------+--------------------+------
  XD0                        | digital in         | 2
  XD1                        | digital in         | 3
  YB5                        | digital out        | 19

5)OR Gate


LADDER DIAGRAM:

   ||                                  ||
   ||       XDO              YB5       ||
 1 ||-------] [------+-------( )-------||
   ||                |                 ||
   ||       XD1      |                 ||
   ||-------] [------+                 ||
   ||                                  ||
   ||                                  ||
   ||                                  ||
   ||------[END]-----------------------||
   ||                                  ||
   ||                                  ||


I/O ASSIGNMENT:

  Name                       | Type               | Pin
 ----------------------------+--------------------+------
  XD1                        | digital in         | 3
  XDO                        | digital in         | 2
  YB5                        | digital out        | 19

6) AND Gate

 LADDER DIAGRAM:

   ||                                                   ||
   ||       XD0              XD1             YPB5       ||
 1 ||-------] [--------------] [--------------( )-------||
   ||                                                   ||
   ||                                                   ||
   ||                                                   ||
   ||------[END]----------------------------------------||
   ||                                                   ||
   ||                                                   ||


I/O ASSIGNMENT:

  Name                       | Type               | Pin
 ----------------------------+--------------------+------
  XD0                        | digital in         | 2
  XD1                        | digital in         | 3
  YPB5                       | digital out        | 19


7)ADC with digital output

LADDER DIAGRAM:

   ||                                  ||
   ||                        A5        ||
 1 ||--------------------{READ ADC}----||
   ||                                  ||
   ||                                  ||
   ||                                  ||
   ||                                  ||
   ||     [A5 <]             YD3       ||
 2 ||-----[ 500]-------------( )-------||
   ||                                  ||
   ||                                  ||
   ||                                  ||
   ||                                  ||
   ||     [A5 >]             YD4       ||
 3 ||-----[ 499]-------------( )-------||
   ||                                  ||
   ||                                  ||
   ||                                  ||
   ||------[END]-----------------------||
   ||                                  ||
   ||                                  ||


I/O ASSIGNMENT:

  Name                       | Type               | Pin
 ----------------------------+--------------------+------
  YD3                        | digital out        | 5
  YD4                        | digital out        | 6
  A5                         | adc input          | 28


8) UART
 Send the letter “J” over uart
LADDER DIAGRAM:

   ||                 ||
   || {A  :=       }  ||
 1 ||-{ 'J'     MOV}--||
   ||                 ||
   ||                 ||
   ||                 ||
   ||                 ||
   ||        A        ||
 2 ||---{UART SEND}---||
   ||                 ||
   ||                 ||
   ||                 ||
   ||------[END]------||
   ||                 ||
   ||                 ||




9) Sending ADC result over UART 
Here i have converted 10-bit ADC result into 8- bit data(ASCII code) by dividing by 4 for proper UART reading
LADDER DIAGRAM:

   ||                                  ||
   ||                        A5        ||
 1 ||--------------------{READ ADC}----||
   ||                                  ||
   ||                                  ||
   ||                                  ||
   ||                                  ||
   ||           {DIV  B  :=}           ||
 2 ||-----------{ A5 / 4   }-----------||
   ||                                  ||
   ||                                  ||
   ||                                  ||
   ||                                  ||
   ||        B                         ||
 3 ||---{UART SEND}---                 ||
   ||                                  ||
   ||                                  ||
   ||                                  ||
   ||                                  ||
   ||                  {D  :=       }  ||
 4 ||------------------{ 13      MOV}--||
   ||                                  ||
   ||                                  ||
   ||                                  ||
   ||                                  ||
   ||        D                         ||
 5 ||---{UART SEND}---                 ||
   ||                                  ||
   ||                                  ||
   ||                                  ||
   ||------[END]-----------------------||
   ||                                  ||
   ||                                  ||


I/O ASSIGNMENT:

  Name                       | Type               | Pin
 ----------------------------+--------------------+------
  A5                         | adc input          | 28
  B                          | UART tx            | 3
  D                          | UART tx            | 3